ECE · RGUKT Basar · Class of 2027

Designing the silicon
that keeps time.

VLSI & FPGA design engineer-in-training. I work across the stack — from transistor-level PLL blocks in Cadence to synthesizable RTL in Verilog — chasing the signal from concept to tape-out.

Verilog / SystemVerilog Cadence Virtuoso / Xcelium RTL-to-GDSII Xilinx FPGA

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SANGA VIGNESH AIR 3868 / GATE'26

About

01 / SUMMARY

I'm a final-year ECE undergraduate at RGUKT Basar, building toward a career in analog/mixed-signal and FPGA design. My recent work centers on an ADPLL research internship at NIT Warangal, where I helped integrate an AI/ML-trained digital filter into a closed-loop phase-locked loop — bridging RTL design with transistor-level mixed-signal verification.

I'm motivated by India's push toward semiconductor self-reliance, and draw inspiration from Dr. A.P.J. Abdul Kalam and Morris Chang. Outside of coursework, I work through full design flows independently — RTL-to-GDSII and FPGA inference pipelines — to build toward placement-ready depth in PLL/clocking and analog design.

HDLVerilog, SystemVerilog, Verilog-A
Analog / Mixed-SignalCadence Virtuoso, Spectre, AMS Designer
Digital FlowGenus, Innovus, ModelSim
VerificationXcelium, JasperGold, Tempus, Conformal
FPGAXilinx Vivado, Artix-7, Spartan-6
ML / Edge AIPython, PyTorch

Internship

02 / EXPERIENCE

RESEARCH INTERN — DEPT. OF ECE

National Institute of Technology, Warangal

May 1 – June 30, 2026

Co-developed an All-Digital Phase-Locked Loop (ADPLL) in UMC 180nm CMOS with an AI/ML-trained 25th-order FIR digital loop filter, coefficients generated via an ANN trained in Python/Colab; co-authored the resulting work under Prof. Patri Sreehari Rao.
Implemented the trained filter as synthesizable Verilog RTL (tapped delay-line FIR, MAC architecture), verified it in Xilinx Vivado, then integrated it with transistor-level TDC, DCO, and frequency-divider blocks via a Verilog-A behavioral model in Cadence Virtuoso.
Verified the full closed-loop ADPLL using Cadence Spectre/AMS Designer — achieving an 8ns lock time, 100ps TDC resolution, and 2.26GHz DCO output at 5.3mW power.

UMC 180nmVerilog-AANN-trained filterCadence Spectre

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Projects

03 / TAPE-OUTS

RTL → GDSII · SCL 180nm

UART RTL-to-GDS

Jun – Jul 2026

Designed a full UART IP (16x-oversampled baud generator, TX/RX FSMs, even-parity framing, 2-flop CDC synchronizer on the async RX line) and carried it through the complete digital ASIC flow: RTL sim → synthesis → GLS/LEC → floorplan → CTS → routing → signoff.
Verified with a self-checking loopback testbench (directed edge cases + 10 randomized bytes) in Xcelium; confirmed RTL-vs-netlist equivalence with Conformal LEC and zero-delay GLS.
Signed off clean across the SS/max and FF/min MCMM corners: 8.275ns worst setup slack, 0 DRC/geometric/routing-overflow violations, and 32.2µW total power (293-cell, pad-framed die).

XceliumGenusInnovusConformal LEC

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FPGA EDGE AI · ARTIX-7

Edge-AI Arrhythmia Detection on FPGA

2026

Built a compact 1D-CNN (4 conv layers + GAP/FC) in PyTorch on the MIT-BIH dataset, using focal loss and weighted sampling to counter ~113:1 class imbalance across 5 beat types.
Hand-wrote a fully custom Verilog RTL accelerator — a reusable, time-multiplexed conv engine driving 8 parallel DSP48E1 MAC lanes — with INT8 weights/activations and BatchNorm fused into the conv layers pre-deployment, targeting an xc7a35t FPGA with no soft-core CPU.
Closed timing at 71.43MHz (WNS +0.086ns) using just 19% LUTs, 10% DSPs, and 33% BRAM; ~82% test accuracy at INT8, 0.111W total on-chip power.

PyTorchDSP48E1INT8 Quant.Vivado

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Education & Certifications

04 / CREDENTIALS

Education

B.Tech, ECERGUKT Basar — GPA 8.40/10 — 2027
Pre-UniversityRGUKT Basar — GPA 9.35/10
Class XSt. Joseph's High School, Hanamakonda — GPA 10.0/10

Certifications

FPGA Arch. for Industrial ApplicationsL&T EduTech — Mar 2026
Hardware Modeling using VerilogNPTEL — Sep 2025
VLSI Chip Design — Electric VLSIL&T EduTech — Feb 2026
Fundamentals of Digital DesignL&T EduTech — Dec 2025
ML for Business AnalyticsWharton School — Aug 2025

Designing the silicon
that keeps time.

About

Internship

National Institute of Technology, Warangal

Projects

UART RTL-to-GDS

Edge-AI Arrhythmia Detection on FPGA

Education & Certifications

Education

Certifications

Marks on the Wafer

Let's build something
that holds timing.

Designing the siliconthat keeps time.

About

Internship

National Institute of Technology, Warangal

Projects

UART RTL-to-GDS

Edge-AI Arrhythmia Detection on FPGA

Education & Certifications

Education

Certifications

Marks on the Wafer

Let's build somethingthat holds timing.

Designing the silicon
that keeps time.

Let's build something
that holds timing.