ECE · RGUKT Basar · Class of 2027

Designing the silicon
that keeps time.

RTL / Digital Design Engineer-in-training, with hands-on depth in FPGA implementation, analog design, and the full RTL-to-GDSII flow. I work across the stack — from synthesizable Verilog RTL to transistor-level PLL blocks in Cadence — chasing the signal from concept to tape-out.

Xilinx Vivado Verilog / SystemVerilog Cadence Virtuoso / Xcelium RTL-to-GDSII

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SANGA VIGNESH AIR 3868 / GATE'26

About

01 / SUMMARY

I'm a final-year ECE undergraduate at RGUKT Basar, building toward a career as an RTL / Digital Design Engineer — with hands-on depth in FPGA implementation and analog design as well. My recent work centers on an ADPLL research internship at NIT Warangal, where I designed the digital loop filter and DCO, Frequency divider blocks and helped close a full mixed-signal PLL loop — bridging RTL design with transistor-level verification.

I'm motivated by India's push toward semiconductor self-reliance, and draw inspiration from Dr. A.P.J. Abdul Kalam and Morris Chang. Outside of coursework, I work through full design flows independently — RTL-to-GDSII, FPGA, and analog/mixed-signal design — sharpening the fundamentals that matter in PLL, clocking, and timing-driven work.

FPGAXilinx Vivado, Artix-7, Spartan-6
HDLVerilog, SystemVerilog, Verilog-A
Analog / Mixed-SignalCadence Virtuoso, Spectre, Cadence AMS
RTL-to-GDS FlowGenus, Innovus, ModelSim
VerificationXcelium, JasperGold, Tempus, Conformal
ML / Edge AIPython, PyTorch

Internship

02 / EXPERIENCE

RESEARCH INTERN — DEPT. OF ECE

National Institute of Technology, Warangal

May – July 2026

Designed a 25th-order FIR digital loop filter as synthesizable Verilog RTL, and a 4-stage ring-oscillator DCO with a TSPC-based ÷64 frequency divider in Cadence Virtuoso, for an ADPLL in UMC 180nm CMOS under Prof. Patri Sreehari Rao.
Integrated the Verilog-A filter model with the transistor-level TDC, DCO, and frequency-divider blocks, closing the full ADPLL loop and demonstrating cross-domain RTL-to-analog integration.
Verified the closed-loop ADPLL mixed-signal design in Cadence Spectre — achieving an 8ns lock time, 2.26GHz output frequency (2.20–2.66GHz tuning range) at 5.3mW, with a 900kHz/bit DCO gain.

UMC 180nmVerilog-AANN-trained filterCadence Spectre

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Projects

03 / TAPE-OUTS

RTL → GDSII · SCL 180nm

UART RTL-to-GDS

Jun – Jul 2026

Designed a UART (TX/RX/baud generator) — a standard peripheral interface block — in Verilog RTL, following a complete RTL-to-GDSII digital design flow.
Performed functional verification with a self-checking testbench on Xcelium; ran RTL-to-netlist equivalence verification with Conformal and zero-delay Gate-Level Simulation with Xcelium.
Synthesized (Genus) and closed timing on SCL 180nm achieving 0 DRC violations and 8.275ns signoff slack — demonstrating strong synthesis and static timing closure fundamentals.

XceliumGenusInnovusConformal LEC

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FPGA EDGE AI · ARTIX-7

Edge-AI Arrhythmia Detection on FPGA

Feb – Mar 2026

Designed custom FSM-based control logic with a pipelined Verilog RTL datapath for real-time 5-class ECG arrhythmia classification (1D-CNN trained in PyTorch, 82% test accuracy on MIT-BIH data).
Developed a self-checking testbench in Xilinx Vivado, debugged simulation waveforms, and verified RTL functionality against a software baseline.
Defined timing constraints (XDC) and closed timing up to 71.43MHz with 0 setup/hold violations on Artix-7 FPGA, using 3,988 LUTs, 4,649 Registers, 9 DSP48E1 slices (10%) and 17 BRAM (33%).

PyTorchDSP48E1INT8 Quant.Vivado

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Education & Certifications

04 / CREDENTIALS

Education

B.Tech, ECERGUKT Basar — GPA 8.40/10 — 2027
Pre-UniversityRGUKT Basar — GPA 9.35/10
Class XSt. Joseph's High School, Hanamakonda — GPA 10.0/10

Certifications

FPGA Arch. for Industrial ApplicationsL&T EduTech — Mar 2026
Hardware Modeling using VerilogNPTEL — Sep 2025
VLSI Chip Design — Electric VLSIL&T EduTech — Feb 2026
Fundamentals of Digital DesignL&T EduTech — Dec 2025
ML for Business AnalyticsWharton School — Aug 2025

06 / CONTACT

Let's build something
that holds timing.

Open to FPGA, Digital, and analog design internships and entry-level roles.

vigneshsangaa@gmail.com GitHub LinkedIn

Designing the siliconthat keeps time.

About

Internship

National Institute of Technology, Warangal

Projects

UART RTL-to-GDS

Edge-AI Arrhythmia Detection on FPGA

Education & Certifications

Education

Certifications

Marks on the Wafer

Let's build somethingthat holds timing.

Designing the silicon
that keeps time.

Let's build something
that holds timing.